1. Field of the Invention
This invention relates generally to improving the interfacial properties between titanium nitride and high density plasma oxide during semiconductor fabrication, and, more particularly, to the use of an engineered interlayer between these two materials in order to improve the stability of the interface during high temperature processing steps.
2. Description of the Related Art
In the manufacture of high performance integrated circuits, many active devices are fabricated on a single substrate. Initially, each of the devices must be electrically isolated during device fabrication. However, later in the process, specific devices must be interconnected in order to effect the desired circuit function. The increasing chip density necessary for very large scale integration (VLSI) and ultra large scale integration (ULSI) devices requires that larger numbers of semiconductor devices, e.g., transistors, be present on the wafer surface, which, in turn, has decreased the area available for surface wiring. As a result, multilevel conductive interconnection schemes are needed. For example, this may be achieved by using multiple levels of sequentially formed metal conduction lines, each level of such lines separated by insulating layer of dielectric material. These dielectric layers are generally known as intermetal dielectrics (IMD) or interlayer dielectrics (ILD). Via holes formed within the layer of dielectric material are filled with a conducting material to form a conductive plug that connects the metal lines formed at different levels.
In one example of forming a multilevel interconnection structure, high density plasma (HDP) oxide, deposited by high density plasma chemical vapor deposition (HDP-CVD), is formed adjacent conductive structures, e.g., conductive lines. High density plasma CVD has become a process of choice for sub-0.5 um intermetal dielectric gap-fill (for example, see Korczynski, E., Solid State Technology, April 1996, pg. 63). A second dielectric, such as a tetraethyl orthosilicate (TEOS) oxide, may be deposited on the surface of the HDP oxide layer. The TEOS layer provides good dielectric properties and can be applied relatively inexpensively by deposition processes that are well established within the industry. The selection of the appropriate dielectric materials for these layers will be governed, for the most part, by cost, performance and operating requirements for a given application.
FIG. 1 is representative of a prior art interconnect structure at an intermediate stage during multilevel interconnect fabrication. Illustrative conductive line 130 is formed by depositing and patterning a layer of conductive material, e.g., aluminum, above the surface 101 of a substrate 100. Intermetal dielectric layers, such as an HDP oxide layer 110 and a TEOS oxide layer 140, are formed as shown in FIG. 1. After etching a via 190, through the TEOS oxide layer 140, and extending to the upper surface 131 of the conductive line 130, it is generally necessary to provide a titanium-titanium nitride (Ti--TiN) barrier system along the sidewalls of the via 190. Thus, after forming the via 190, a layer of titanium 150 is deposited in the via 190. Titanium provides good ohmic contact with the underlying conductive line 130, and also serves as an adhesion layer between the conducting metal 180, e.g., tungsten, and the sides of the via 190. However, as the titanium layer 150 is very reactive, and subsequent tungsten deposition can damage the exposed titanium, a titanium nitride (TiN) layer 160 is deposited on the surface of the titanium layer 150. Thus, the sidewalls of the via 190, in addition to a portion of the upper surface 131 of the conductive line 130 exposed by the via 190, are coated with a titanium-titanium nitride barrier layer. The via 190 is thereafter filled with a conducting metal 180, such as tungsten, resulting in the tungsten plug interconnection structure depicted in FIG. 1. By repeating the above process, a multilevel interconnect structure comprising alternating layers of conductive lines and conductive plugs may be formed above the surface of the wafer.
During the formation of such multilevel interconnections, there is a propensity for defect formation when HDP oxide and titanium nitride are used in the same process. During certain of the process operations described in the above fabrication sequence, the semiconductor wafer is clamped along its outer circumference, and materials are thereby prevented from contacting the surfaces along the wafer edge that are covered by the clamps. With reference to FIG. 2, these clamps (not shown) generally contact the wafer 201 along its edge 200 and may extend for a distance of about 3-5 mm, or greater, inward from the edge 200 of the wafer substrate 201. The clamps may contact the wafer in any of a number of configurations. Some clamps may contact the wafer around its entire circumference, while other clamps may utilize finger-like projections at a plurality of positions along the wafer edge 200. Regardless of clamp configuration, the regions along the edge of the wafer 201 that are contacted by the clamp are shielded from the processing materials to which the wafer 201 is exposed in a given fabrication process. For example, because the wafer 201 is clamped during a titanium deposition process, titanium is not deposited along the edge 200 of the wafer 201 that is contacted by the clamp. However, during other processing steps, such as formation of HDP oxide, TEOS oxide, and titanium nitride, the edge 200 of the wafer 201 may be unclamped. Consequently, during these processes, materials do contact the surface of the wafer 201 along the edge 200, and have a tendency to accumulate thereon. For example, as depicted in FIG. 2, layers of titanium nitride 210, HDP oxide 220 and TEOS oxide 230 form along wafer edge 200 during processing. This occurs many times over as multilevel interconnect fabrication proceeds.
This situation can be problematic during subsequent processing steps because of the poor interfacial properties between HDP oxide and titanium nitride. In particular, subsequent high temperature processing steps can result in delamination at the titanium nitride/HDP oxide interface, causing bubbling to occur in localized regions along the wafer edge where this delamination occurs. These regions can burst open and release small oxide discs as airborne projectiles which land randomly on the wafer surface, causing die loss and adversely effecting process yield.
The present invention is directed to overcoming, or at least reducing the effects of, the problems set forth above.